The present invention relates particularly to a semiconductor integrated circuit device comprising a memory such as a DRAM (dynamic RAM) for accompanying refreshing operations.
FIG. 1 is a block diagram showing a conventional row system address generator of a DRAM. When activating word lines WL in order to input and output data to/from the DRAM, a row address signal RA which specifies a given word line and a row address strobe signal /RAS (in the diagram, the header / is indicated by bar above) are input.
The /RAS is temporarily stored in a row address controller 12. Next, when a clock signal (not shown in the diagram) has been input to the row address controller 12, a control signal is sent from the row address controller 12 to a row address buffer 11. The row address buffer 11 receives this control signal and passes on the row address signal RA which has been temporarily stored in the row address buffer 11.
Thereafter, the row address signal RA is transmitted via a multiplexer (also known as an address multiplexer) 13, which multiplexes the row address signal RA with a refresh address signal, a row pre-decoder 14, a row decoder 15 and a word line driver 19, thereby activating the word line WL. Furthermore, those addresses which are not required for refreshing are input directly to the row pre-decoder 14 without passing through the multiplexer 13 (10).
On the other hand, when carrying out refresh operations, a refresh signal REF sent from the outside becomes active and is input to a refresh controller 16. The REF signal causes the refresh controller 16 to supply a control signal in synchronism with a clock signal (not shown in the diagram) to a refresh counter 17 and to the row address buffer 11 and the multiplexer 13. As a consequence, the multiplexer 13 switches from inputting addresses from the row address buffer 11 to inputting refresh addresses from the refresh counter 17. That is, the refresh counter 17 commences operation and the output from the address multiplexer 13 is switched to the value of the refresh counter 17. The refresh address signal sent from the refresh counter 17 passes through the row pre-decoder 14, the row decoder 15 and the word line driver 19, thereby activating the word line WL. Further, those address signals (10) which are not input to the multiplexer 13 all switch to "H" (high level) at the row address buffer 11. Furthermore, the value of the refresh counter 17 is incremented each time a refresh signal REF is input thereto.
FIG. 2 is a schematic block diagram showing the configuration of primary parts of a conventional DRAM having the structure described above. The DRAM has capacity of 2.5 megabits, and 256 row lines, that is, word lines (WL) which are not shown in the diagram, are provided for each cell array block (256k cell array). Sense amplifiers are provided next to each cell array. The sense amplifiers S/A on either side of each cell array are connected in alternate sequence by pairs of bit lines. Moreover, the sense amplifiers provided between the cell arrays are shared sense amplifiers which can be used by the cell arrays on either side thereof. That is, each sense amplifier S/A comprises switch-connecting means for electrically isolating the pairs of bit lines of the cell array on either side. However, the sense amplifiers between cell arrays (4) and (5) are individually provided and cannot be shared.
Firstly, the method of accessing (for instance, reading out from) the memory cells when writing and reading (write/read) according to the configuration described above will be explained. In write/read operations, two word lines are activated in correspondence with one row address. Combinations of 256k cell arrays whose word lines become active simultaneously is: (0) and (5), (1) and (6), (2) and (7), (3) and (8), (4) and (9). Since two word lines connect to each cell, a column address determines from which cell data are to be read out. Row address signals A0 to A7 determine which word line (one out of 256 word lines) is to be activated in each 256k cell array.
Row address signals A8 to A10 select 256k cell arrays. That is, they select two 256k cell arrays, whose word lines become active simultaneously in the combinations described above, in correspondence with the connection concept of FIG. 2 showing address decodes for A8 to A10. Therefore, in the present example, the number of row addresses is 256.times.5=1280.
Next, the refresh operation in the configuration shown in FIG. 2 will be explained. When refreshing, the row addresses select 512 word lines. Refreshing is carried out by raising address signals /A10, A10, /A9 and A9 to "H" (high level; "1"). (In the diagram, the address signal headers / have bars thereabove.) The word lines which are activated during refreshing are determined only by address signals A0 to A8. For instance, when all the row address signals A0 to A8 are at the low level ("0"), the 0 word lines WL0 of the 256k cell arrays (0), (2), (4), (5), (7) and (9) are simultaneously activated. Thereafter, the refresh counter activates the word lines sequentially and refreshing is carried out as far as word lines WL255. After this, when row address signals A0 to A7 are all still at "L" (low level; "0") and row address signal A8 has risen to "H" (high level; "1"), the 0 word lines WL0 of the remaining 256k cell arrays (1), (3), (6) and (8) are simultaneously activated. Thereafter, the refresh counter sequentially activates the word lines and the cell arrays are refreshed as far as until word lines WL255. In this way, all cell arrays in the memory can be refreshed using 512 addresses corresponding to word lines WL0 to WL511, which is equivalent to two cell arrays.
In a refresh operation by the method according to the above configuration, word lines of cell array (4) and cell array (5) are activated simultaneously. Therefore, it is not possible to provide a shared sense amplifier between the cell arrays (4) and (5). As a consequence, as illustrated by sense amplifier (4) and sense amplifier (5) of FIG. 2, sense amplifiers must be provided separately, causing a problem of increased layout size.
Furthermore, in a memory such as an ASIC (application specific IC) embedded DRAM, there is a demand to increase the number of memory cells as much as possible with refresh units (of 512 word lines in this case) in order to achieve a desired capacity. When the conventional technology described above is used in an attempt to realize this, 256k cell arrays (4) and (9) require a different layout configuration from the other parts, which is a disadvantage from the point of view of increasing capacity.